1. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly, the present invention relates to circuits and methods for regulating the output voltage of a charge-pump circuit used in a semiconductor integrated circuit.
2. Description of the Related Art
Semiconductor devices generally operate using a variety of internal voltages. For example, electrically-erasable-programmable non-volatile memory devices utilize a voltage exceeding a power supply voltage when conducting erasing and programming operations. This high voltage, or boosted voltage, is generally supplied by a charge-pump circuit.
FIG. 1 is a block diagram of a conventional charge-pump circuit 100. The charge-pump circuit 100 includes a regulator 110, a pumping unit 130, and a clock control unit 150.
The regulator 110 includes a sensing unit 111 (implemented as a voltage divider with resistors RA and RB) and a comparison unit 113 (implemented as a differential amplifier driven by a supply voltage VDD and receiving a bias voltage VB). The regulator 110 senses a pumping voltage VREG output from the pumping unit 130 and maintains the pumping voltage VREG at a target high voltage. In particular, the sensing unit 111 outputs a sensed voltage VSENSE based on the pumping voltage VREG, and the comparison unit 113 causes the clock control unit 150 to activate the pumping unit 130 when the sensed voltage VSENSE is less than a reference voltage VREF, and to not activate the pumping unit 130 when the sensed voltage VSENSE is equal to or greater than the reference voltage VREF.
The clock control unit 150 receives a clock signal CLK and is responsive to the output of the regulator 110 to output the clock signal CLK as a controlled clock signal CLK_CTRL. In particular, the clock signal CLK (i.e., the controlled clock signal CLK_CTRL) is supplied to the pumping unit 130 only when the regulator 110 indicates that the sensed voltage VSENSE is less than the reference voltage VREF.
The pumping unit 130 is responsive to the controlled clock signal CLK_CTRL to output the pumping voltage VREG. The pumping unit 130 generates the pumping voltage VREG (which is higher than a power supply voltage VDD) by continuing or discontinuing a voltage pumping action according to the controlled clock signal CLK_CTRL. More particularly, when the pumping voltage VREG is less than the target high voltage (i.e., indicated by the sensed voltage VSENSE being less than the reference voltage VREF), the voltage pumping action continues in response to an ON-state of the controlled clock signal CLK_CTRL. On the other hand, when the pumping voltage VREG is equal to or greater than the target high voltage (i.e., indicated by the sensed voltage VSENSE being equal to or greater than the reference voltage VREF), the voltage pumping action is temporarily discontinued in response to an OFF-state of controlled clock signal CLK_CTRL.
As described above, the regulator 110 senses the pumping voltage VREG, generates a corresponding sensed voltage VSENSE, and controls activation and deactivation of the pumping unit 130 by comparing the sensed voltage VSENSE with the reference voltage VREF. Disadvantageously, a timing delay occurs between a time at which the regulator 110 senses the pumping voltage VREG and compares the same with the reference voltage VREF, and a time at which the voltage pumping action of the pumping unit 130 is controlled. This delay is primarily caused by a resistor-capacitor (RC) delay in the regulator 110.
Referring to FIG. 1, the resistance value of the resistor RA is generally much greater than the resistance value of a resistor RB. When the pumping voltage VREG is sensed and input as the sensed voltage VSENSE to the comparison unit 113, the sensed voltage VSENSE exhibits a relatively long RC delay caused by inter-capacitance and the high resistance of resistor RA.
FIG. 2 is a timing chart illustrating a pumping voltage relative to the target high voltage VTARGET. As shown in FIG. 2, a voltage ripple occurs in which actual pumping voltage overshoots the target high voltage VTARGET. This is caused by the high pumping capacity of the pumping unit 130 and the delay within the regulator 110, especially the resistor-capacitor (RC) delay of the regulator 110. The pumping unit 130 generally requires a high pumping capacity in order to rapidly increase the pumping voltage to the target high voltage VTARGET when starting a pumping operation. However, this high pumping capacity, coupled with the RC delay of the regulator 110, can cause substantial overshooting of the target high voltage VTARGET.